Presentation Descriptions

Sponsored Tutorials

By: Mentor, a Siemens Business, United States

Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration. We will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before. 

By: Product Management, United States

In this workshop, learn why you should consider bridging emulation and prototyping into a continuous verification environment to speed up your verification throughput for early software validation and real world testing. This workshop will cover: • Fast design bring up between platforms (e.g. common implementation flow, common look & feel UI) • Advanced debug (e.g. FullVision engine, probes, memory force and release, etc.) • Re-usable system-level interfaces (real-world testing) 

By: Breker Verification Systems, United States
Cadence Design Systems, United States
Mentor, a Siemens Business, United States
Synopsys, United States
Vayavya Labs, India

The Portable Test and Stimulus Standard (PSS) from Accellera lets you create a single representation of stimulus and test scenarios that are usable by a variety of users across different platforms and different integration levels throughout a verification project. This tutorial will share some of the important new features coming in v2.0 that were added to enhance the usability, programmability and portability of PSS.

By: Amazon, United States
Synopsys, United States

In this tutorial, architects from AWS, verification experts from Synopsys, and customers running simulation on the cloud will discuss these challenges and demonstrate a software development kit (SDK) including all the scripts required to setup a complete verification environment on the AWS. A joint solution between AWS and Synopsys has been developed to help customers bring their verification environments to AWS. This hands-on tutorial will include all the components essential to develop, compile, run and debug simulations in a cloud environment optimized for verification workloads. We will demonstrate how customers can easily deploy the Synopsys Verification Continuum® platform on AWS, making it easy to select the compute architecture of their choice, such as AMD EPYC, Arm-based AWS Graviton2, or Intel Xeon processors. 

Sponsored Workshops

By: Marketing, United States
Solutions Architect, India

In this workshop, we will take the attendees through using the JasperGold Superlint and CDC applications, which add formal verification technology and functional checks to these structural checks. The JasperGold technology supports the designers to identify the real problem violations, confirming fixes, and providing justification for waiving the violations that are not problematic. Additional automatic formal checks are provided for functional verification of many aspects of the design, using properties derived automatically from the RTL. Workshop attendees will learn how these JasperGold RTL Designer apps combine to “shift left” these checks, providing a much more complete level of automated verification. The result is that RTL designers are able to sign off higher quality, more robust and CDC/RDC-clean designs, months earlier in the project schedule. 

By: Optima Design Automation, India; Optima Design Automation, Israel

Automotive Functional Safety Analysis under the ISO 26262 standard has evolved over the last few years, as the challenges have become better understood and respective solutions refined. Early approaches to demonstrate that devices meet specific Automotive Safety Integrity Level (ASIL) requirements have given way to more effective techniques and technologies. In this workshop we present new solutions that accelerate and increase the accuracy of this development phase.

By: Cadence, United States

Accellera formed a working group of functional safety practitioners and experts from the industry to develop a standard that will provide a standardization definition of the Functional Safety data exchange to improve automation, interoperability, and traceability of the implementation of the Functional Safety guidelines and best practices during the lifecycle. The standard plans to capture a data model, language, or format to exchange data seamlessly among functional safety work products and across layers of the supply chain. This workshop presents some of the challenges in the industry for managing the exchange of data related to functional safety and then the goals and mission of the Accellera Functional Safety Working Group towards a new standard to address those challenges.

By: OneSpin Solutions, Germany

This workshop will explore how mutation analysis can have a positive impact on the safety of your design and provide the signoff confidence needed to achieve proper safety certification. In addition, the workshop will show how to achieve a meaningful integration of formal and simulation coverage metrics. A long-standing wish of many verification engineers and managers, coverage integration reduces effort overlap between simulation and formal and enables faster, more rigorous signoff.

By: Mentor, A Siemens Business, United States

This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology. Finally we will present 2-3 customer case-studies showcasing how these technologies work in conjunction to address our customers HLS design and verification challenges.

By: Circuitsutra Technologies Pvt Ltd, India

The term ‘Electronics System Level (ESL)’ have been used in the industry for nearly two decades now. Different people use it in different context, with different meanings. It can be primarily generalized as the collection of methodologies that enables ‘Hardware-Software Co-Design’ and ‘Raising the abstraction of chip design above RTL’. ESL methodologies are not supposed to replace the traditional RTL-GDS flow, but rather co-exist with existing flow and augment it to perform various advanced activities which are not feasible with traditional flow. It enables Pre-Silicon firmware development, Architecture exploration to optimize power & performance early in the cycle at system level, High-Level Synthesis (HLS), SoC Level simulation, System level simulation, Hardware-Software co-design and co-verification. In this workshop we will briefly touch upon various use cases of ESL methodologies and discuss the best practices being used in the industry. 

By: Mentor Siemens, United Kingdom

In this workshop, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture. We will outline a methodology which includes local intelligence inside the SoC to select and communicate off-chip only those monitoring data which are significant and meaningful. In this workshop, we will further discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process. 

By: Breker Verification Systems, United States

SoC Verification has become more important in recent years. However, this task is challenging given the increased complexity of UVM for larger systems, emulation usage and the need to drive processors as part of the system. This tutorial will provide a methodology using a virtual realization layer, as suggested by the PSS committee, which can perform various OS-like capabilities while streamlining hardware verification tool usage. It may also be used to aid firmware verification with the hardware.

By: Intel, United States
Onespin, United States

This session will introduce an emerging new standard called Security Annotation for Electronic Design Integration (SA-EDI) to address security concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to provide information about the IP security relevant to the integrator and recommended mitigations to implement and risk to address.  At the conclusion of this session, attendees will better understand risks associated with IP and become familiar with the SA-EDI standard, including how it can be applied and when it will be available for reference.

By: Semifore, United States

The tape out used to be the end of a chip design project. Now, it’s just the beginning. The chip needs to work in the system. And that means hardware, software, firmware, third party IP and exotic packaging technology all need to work in harmony. Today’s SoCs are highly complex endeavors involving many contributors from many different disciplines. And they all need to be coordinated.

In this short workshop, we’ll explore the challenges of harmonizing hardware and software design for SoC projects. The format will be informal conversations with three experts in this field. Josh Rensch from Semifore will do the interviewing. He’ll be talking with Dave Burgoon, Principal Design Verification Engineer at Microsoft Corporation, Richard Weber, Co-Founder and CEO at Semifore and Jamsheed Agahi, Co-Founder and VP Quality at Semifore.

During these interviews, the speakers will share their real-life perspectives regarding hardware/software design – what’s important and what they learned. We’ll also touch on standards. Where they work and where they fall short. Attendees with gain relevant, actionable information to help them with their next design project as well as have the opportunity to talk live with all panelists during a lively Q&A session after the interviews.

By: AMD, United States
Cadence, Israel
Intel, United States
NXP, Netherlands

In this short workshop, the MLVWG presents the current status of the proof-of-concept implementation and demonstrate its capabilities. A multi-language example is presented, which combines the Universal Verification Methodology (UVM) library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language-specific UVM standardization requirements will be presented and language extensions are proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.

By: Agnisys, Inc., United States

RISC-V brings a new wave to SoC development. Creating a fully validated design is an arduous process that takes several teams working together. Often the flow is a waterfall model where the specification is transformed in various stages of development. Sometimes aspects such as verification and validation are an afterthought. In order to speed up the process and get better quality of results, all aspects must be considered upfront.

By: AMD, United States
Google, LLC, United States

Silicon design is getting more complex, but time-to-market schedules are shrinking. Design teams have to do more with the same number of engineers. Companies engaged in designing chips are finding it challenging to absorb the increasing complexity while meeting schedule demands. Inherent benefits of the cloud, such as elasticity, fault tolerance, and security can be successfully leveraged by design teams.At this workshop you will learn basics of getting your EDA workloads running on Google Cloud Platform, and understand some real world use cases.

By: Tessolve, United Kingdom

Short Workshop on RiscV Verif - from core to SoC

By: Engineering, United States

This workshop will demonstrate methods for addressing throughput, analysis efficiency and traceability utilizing features provided in the latest, fourth generation, architecture of Cadence vManager Verification Management solution. Specific solutions addressed will include supporting geographically distributed verification teams, cloud based regression farms, auto failure classification, open verification data APIs, and robust connections to functional specifications and requirements management systems.

By: IBM, United States
North Carolina State University, United States
Si2, United States
Thrace Systems, United States

This workshop will describe the new power modeling standard, IEEE 2416, the novel tools and methodologies it enables, and the inter-operation of 2416 power data models with IEEE 1801 power state models. 2416 addresses the power modeling needs of three distinct groups of users:  IP providers, System Architects and System Validation teams, and EDA developers.  Use of 2416 by each group will be described using a memory model and a RISC-V processor model with an Energy per Instruction format.

By: Cadence, United States
NXP, United States
Qualcomm, United States
Xilinx, United States

Key members of the Accellera UVM-AMS Working Group will share the work done so far in developing a comprehensive and unified analog/mixed-signal verification methodology based on UVM to improve analog mixed signal (AMS) and digital mixed signal (DMS) verification of integrated circuits and systems.

By: Cosida Technologies GmbH, Germany

This workshop will introduce the basic concepts of UVM-SystemC and show how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the Accellera VWG is working on the standardization of a common randomization layer based on CRAVE, a C++, and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.

By: Veriest Solutions, Israel

This presentation is addressing the handling of random failures during the design and verification of the CEVA IPs designed to be parts of a complex automotive system. By analyzing architectural aspects of modern integrated circuits we will identify critical design features and we will review principles for verification of safety mechanisms based on an example of an AI processor for on-chip deep learning inferencing, computer vision tasks, and fusing data from multiple sensors such as radar, lidar, time-of-flight, microphones, and other inertial measurement units.


By: AMD, United States
Google LLC, United States
Semiconductor Engineering, United States
SiFive, United States
Synopsys, United States

Gartner predicts that by 2025, about 80% of the datacenters will move to the cloud. Inherent benefits of the cloud, such as elasticity, fault tolerance, and security cannot be matched by on premise data centers. Indeed, cloud is the datacenter of choice for several industries from retail to banking to manufacturing.Chip design and verification on cloud has been a topic for decades (many among us remember the efforts of EDA companies in the early 2000s). However, the cloud - as it is today - is stunningly different. But what is the state of chip design on cloud? Are companies designing successfully on the cloud? Are migration efforts underway at companies? What works? What doesn’t? Hear from a panel of designers and infrastructure experts on their experience with cloud. Learn about what works, what doesn’t work or what cannot work! 

By: Nanette V. Collins Marketing and Public Relations, United States

The idea of open source hardware, such as RISC-V that anyone can leverage to create their own CPU or custom accelerator, is tantalizing. Supporters believe freely available solutions will break open processor innovation and enable entry into new market segments.  Verification groups are hopeful but leery knowing verification is more complex than design. Most open source hardware is new, which means verification groups are on the line to devise an untried verification flow.  Design verification experts and open source proponents will analyze verification challenges and discuss what compliance mean, how it is defined and whether it requires open source verification environments.