Dr Paul Cunningham
Date: March 2nd
Time: 13:00-14:15 PST
Registration Access Level: Exhibits, Panel & Keynote ONLY
Computational Logistics for System and Software Verification
Abstract: Modern SoC designs are complex multi-billion gate compute systems containing multi-core CPUs, GPUs, DSPs, multimedia accelerators, and AI accelerators. Verification of these devices and their software stacks requires a new throughput-centric mindset that considers the cost of tools, compute, and people, as well as the relative abilities of each, to accelerate verification. In this talk, Dr. Cunningham will introduce the concept of verification throughput and highlight the significant opportunities we have as an industry to dramatically improve verification throughput on modern SoC designs.
Bio: Paul Cunningham is corporate vice president and general manager of the system verification group at Cadence. His product responsibilities include logic simulation, emulation, prototyping, formal verification, Verification IP, and debug. Prior to this, he was responsible for Cadence's frontend digital design tools including logic synthesis and design-for-test. Paul joined Cadence in 2011 through the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO.
Paul holds a Master's Degree and a Ph.D. in Computer Science from the University of Cambridge in the UK.
