DVCon U.S. 2021 Announces Stuart Sutherland Best Paper & Best Poster Winners, Attendance Numbers
“We are very pleased with the attendance during our virtual conference this year,” stated Aparna Dey, DVCon U.S. General Chair. "DVCon continues to be a resource for the practicing design and verification engineer and there were many valuable sessions to choose from. We had a record number of workshops this year, lively question and answer sessions following many of the presentations and 20 exhibitors for attendees to choose from. I would like to extend my sincere thank you to our steering committee, Conference Catalysts and Accellera for an outstanding virtual conference this year. I’d also like to congratulate our paper and poster winners for their excellent presentations.”
The award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to Ping Yeung, Mark Eslinger, and Jin Hou, Siemens EDA, for their presentation, “Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt.” Second place was awarded to Cliff Cummings, Stephen Donofrio and Jeff Wilcox of Paradigm Works and Heath Chambers, HMC Design Verification for their paper, "Advanced UVM, Multi-interface, Reactive Stimulus Techniques.” Third place was awarded to Ioana Catalina Cristea and Dragos Dospinescu, Amiq Consulting for their paper, "Open-Source Framework for Co-Emulation Using PYNQ."
Top honors for Best Poster went to David Barahona, Motaz Thiab and Milica Orlandic, Norwegian University of Science and Technology and Isael Diaz and Joakim Urdahl, Nordic Semiconductor for their poster, “Improving Software Testing Speed by 100X with System C Virtualization in IoT Devices.” Second place was awarded to Gabriel Pachiana, Maxamillian Grundwald, Thomas Markwirth, and Christoph Sohrmann, Fraunhofer IIS/EAS for their poster, “Automated Traceability of Requirements in the Verification Process of Safety-Critical Mixed-Signal Systems.” Third place was awarded to Jian-Hua Yan, MediaTek Inc., and Ping Yeung, Stewart Li, and Sulabh-Kumar Khare of Siemens EDA for their poster, “Preventing Glitch Nightmares on CDC Paths: The Three Witches.”
“I’d like to congratulate all of our paper and poster winners this year,” stated Vanessa Cooper, DVCon U.S. Technical Program Committee Chair. "Each presenter worked very hard to bring content to our attendees that would be valuable in their day-to-day jobs, helping them to be even more successful. We had a variety of presentations on topics ranging from RISC-V to UVM, to Machine Learning and security and all were well-attended. I would also like to thank the TPC for their efforts in putting together an information-rich program on a virtual platform. The committee put in a great deal of time over many months planning an outstanding 2021 technical program for our attendees.”
Highlights of the Week:
- A record number of short workshops were available to attendees this year, with 12 held on Monday and six on Thursday. The workshops give attendees an opportunity to learn from a broader set of vendors, including smaller companies.
- The keynote on Tuesday, presented by Dr. Paul Cunningham, corporate vice president and general manager in the System & Verification Group at Cadence Design Systems, Inc., focused on the concept of verification throughput and the opportunities we have as an industry to dramatically improve verification throughput on modern SoC designs.
- Accellera honored Matthew Ballance, one of the earliest and most frequent contributors to the Portable Test and Stimulus standard, with the 2021 Technical Excellence Award during a virtual presentation following the keynote. Matthew is a member of the Portable Stimulus Working Group and a Product Engineer and Portable Stimulus Technologist with Siemens Digital Industries Software.
- There were two thought-provoking panels on Wednesday. The first panel, “Verification in the Open-Source Era,” covered the various ideas on what open-source verification means, whether or not it’s truly free and the potential ramifications. There was spirited conversation among the panelists as they discussed the various issues and potential solutions. The second panel, “Chip Design on Cloud—From Pipe Dream to Preeminence?” had a very lively discussion among panelists about how companies are approaching the security issues of designing on the cloud, what works and what does not and where the industry might be headed.
The conference sessions are available for all-access registered attendees to view through March 31, 2021.
Save the date: DVCon U.S. 2022 will be held February 28 - March 3, 2022 at the DoubleTree Hotel in San Jose, California.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.
For more information, please contact:
Laura LeBlanc Barbara Benjamin
Conference Catalysts, LLC HighPointe Communications
352-872-5544 Ext. 115 503-209-2323
[email protected] [email protected]
