Sponsored Engagement/Networking Schedule

16:00 PST

  • AMIQ Networking
  • Corigine, Inc. (Corigine’s next-generation Prototyping solution)
  • Metrics Design Automation (Cloud-Based Regression Acceleration with Metrics)
  • Scientific Analog, Inc. (Meet XMODEL: The Best Way to Verify Analog Circuits in SystemVerilog)

16:30 PST

  • Verification Technology Inc. Networking
  • Agnisys, Inc. Networking

14:00 PST

  • Corigine, Inc. (Corigine’s next-generation Prototyping solution)
  • Metrics Design Automation (Cloud-Based Regression Acceleration with Metrics)
  • Semifore (Standards for the hardware/software interface - what works, what falls short)
  • Synopsys Networking (Advanced Integrated Development Environment for SoC Design and Verification)
  • Verifyter (How does an Automatic Debugger work?)

14:30 PST

  • AMIQ Networking
  • Breker Verification Systems (SoC/UVM Test Content Synthesis Discussion)
  • Imperas (25 years after Verisity, verification is still evolving)
  • Rescale (Cloud SoC Design & Verification)
  • Siemens (Extending the Role of Test to meet Automotive Safety and Security Requirements)

15:00 PST

  • Blue Pearl Software Networking
  • Accelver Systems Inc. Networking
  • Cadence Networking with Juergen Jaeger

15:30 PST

  • Avery Design Systems (Advanced PCIe and CXL Verification Methods )
  • Siemens (Market Driving Trends in Hardware Emulation)

16:00 PST

  • Imperas (A personal perspective on the history of SystemVerilog / Superlog)
  • Scientific Analog, Inc. (Meet XMODEL: The Best Way to Verify Analog Circuits in SystemVerilog)
  • Synopsys Networking (Datapath Validation Using Formal Techniques)

14:00 PST

  • AMIQ Networking
  • Imperas (Advanced Processor verification in the era of open ISA’s – is flexibility testing the limits of DV)
  • Siemens (Trends in Functional Verification)
  • Sigasi Networking
  • Synopsys Networking (The New Power Perspective - Realistic Workloads - Real Results)
  • Cadence Networking with Matt Graham

14:30 PST

  • Breker Verification Systems (Portable Stimulus Apps Reduce the Learning Curve)
  • Rescale (Cloud SoC Design & Verification)
  • Semifore (Standards for the hardware/software interface - what works, what falls short)
  • Sigasi Networking

17:00 PST

  • Circuitsutra Technologies Pvt Ltd (Shift-Left using SystemC)
  • Synopsys Networking (Advanced Integrated Development Environment for SoC Design and Verification)

17:30 PST

  • Verification Technology Inc. Networking
  • Blue Pearl Software Networking

12:30 PST

  • Avery Design Systems (SimXACT X-Verification)
  • Circuitsutra Technologies Pvt Ltd (SystemC Methodology for RISC-V Ecosystem)
  • OneSpin Solutions (AMA With OneSpin’s Application Engineers)
  • Verifyter (Automatic Debug using ML)

13:00 PST

  • OneSpin Solutions (AMA With OneSpin’s Application Engineers)
  • Blue Pearl Software Networking
  • Accelver Systems Inc. Networking