Welcome to DVCon U.S. 2021
The Design and Verification Conference & Exhibition
Welcome to the DVCon U.S. 2021 Virtual Conference!
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design
Final presentations and content will be due on February 9th for Authors, Speakers, Exhibitors, and Sponsors. This is a hard deadline and NO extensions will be provided. Please visit your corresponding page and check your email for more information.
Calling all Authors
Call for Extended Abstracts
Abstract Submission Deadline EXTENDED to September 8th!
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows. This year the conference will be completely virtual.
In addition to the specific topic areas suggested below, submissions may incorporate:
- Usage of Electronic Design Automation (EDA) tools such as simulation, emulation, formal verification, virtual prototyping and/or FPGA prototyping
- FPGA-based designs
- Usage of specialized design and verification languages such as SystemVerilog, SystemC, and e
- Assertions in SVA or PSL
- The use of general purpose and scripting languages such as C, C++,Perl, Python, Tcl and others
- Applications of the Accellera Portable Stimulus Standard
- Applications of design patterns or other innovative language techniques
- The use of AMS languages
- Internet of Things applications
Accepted authors will be invited and agree to do the following:
- Submit a draft paper between October 26 and November 15 for review.
- Review and incorporate feedback from TPC, to be provided by November 20.
- Submit a final paper and copyright form by December 14.
- Submit a recorded oral or poster presentation for presentation at the virtual conference by February 9.
Find & plan
DVCon U.S. 2021 Schedule
Find and plan out your virtual experience on the DVCon U.S. 2021 schedule!
DVCon U.S. 2021
The Design and Verification Conference (DVCon)
March 1-4, 2021 | San Jose, CA, USA