Date: March 3rd
Time: 8:30-9:30 PST
Registration Access Level: Exhibits, Panel & Keynote ONLY
Nanette V. Collins Marketing & PR
Jean-Marie Brunet/Siemens EDA
The idea of open source hardware, such as RISC-V that anyone can leverage to create their own CPU or custom accelerator, is tantalizing. Supporters believe freely available solutions will break open processor innovation and enable entry into new market segments. Blocks of open source IP already are implemented or in the process of being implemented in many of today’s chip designs. Success seems assured.
Verification groups are hopeful but leery knowing verification is a much more complex problem than design. Most open source hardware is new and does not have the benefit of field-proven experience, which means verification groups are on the line to devise an untried verification flow, making a well-considered CPU verification strategy fundamental. Without those ingredients, it is impossible to have confidence in verification results.
Semiconductor Engineering’s Brian Bailey will take a panel of design verification experts and open source proponents on an excursion into the open-source era to analyze the verification challenges. His questions, meant to create debate and discussion, will include:
- Is open source verification more or less complex than design?
- Does open source verification mean that an engineer creates a SystemVerilog testbench and makes it freely available?
- Should the industry have a freely available open source reference model?
- The formal model for the RISC-V processor is written in SAIL, a language not traditionally supported by the EDA community. Will this lead to a departure in tool development?
- Some believe that for true open source, open source tools need to be available. Who will supply the funding for this development when major players already pay for the necessary tools?
- Can open source tools compete with tools that have seen long-term investment?
- What does compliance mean and how will it be enforced? Does compliance require open source verification environments? If so, what they would look like?
- Most processors are verified with a combination of formal and simulation methods? How will formal play in an open source world?
By the panel’s conclusion, panelists will have attempted to answer why verification is essential for success of the open source movement.
Question for positioning statement: What does open source verification mean?