Early Design and Validation of an Ai Accelerator’s System Level Performance Using an HLS Design Methodology


Date: March 1st 
Time: 13:30-14:30 PST
Registration Access Level: ALL-ACCESS 

By: Michael Fingeroff, Mentor, A Siemens Business

This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology. Finally we will present 2-3 customer case-studies showcasing how these technologies work in conjunction to address our customers HLS design and verification challenges.

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