Multi Language Verification Framework Standardization and Demo


Date: March 1st 
Time: 11:30-12:30 PST
Registration Access Level: ALL-ACCESS 

By: Warren Stapleton, AMD; Bryan Sniderman, AMD; Alex Chudnovsky, Cadence; Faris Khundakjie, Intel; Martin Barnasconi, NXP

In this short workshop, the MLVWG presents the current status of the proof-of-concept implementation and demonstrate its capabilities. A multi-language example is presented, which combines the Universal Verification Methodology (UVM) library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language-specific UVM standardization requirements will be presented and language extensions are proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.

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