Workshop
Abstract
Date: March 4th
Time: 11:30-12:30 PST
Registration Access Level: ALL-ACCESS
By: Anupam Bakshi, Agnisys, Inc.; Abhishek Bora, Agnisys, Inc.
RISC-V brings a new wave to SoC development. Creating a fully validated design is an arduous process that takes several teams working together. Often the flow is a waterfall model where the specification is transformed in various stages of development. Sometimes aspects such as verification and validation are an afterthought. In order to speed up the process and get better quality of results, all aspects must be considered upfront.
