Date: March 1st
Time: 9:00-10:00 PST
Registration Access Level: ALL-ACCESS
- - Thilo Vörtler, Coseda Technologies, Dresden, Germany, [email protected]
- - Dragos Dospinescu, AMIQ [email protected]
Contributions to the short workshop presentation are also provided by:
- - Martin Barnasconi, NXP Semiconductors
- - Stephan Gerth, Bosch Sensortec GmbH
UVM-SystemC is an implementation of the Accellera UVM standard implemented in SystemC. Standardization efforts of UVM-SystemC is ongoing and multiple public review releases were released in the past years. Currently, the Accellera VWG is working on the standardization of a common randomization layer and a definition of functional coverage for UVM SystemC.
This tutorial will introduce the basic concepts of UVM-SystemC and show how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the Accellera VWG is working on the standardization of a common randomization layer based on CRAVE, a C++, and SystemC constraint randomization library. The tutorial will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments. Furthermore, the functional coverage library “fc4sc”, which has also been donated to Accellera will be presented.
In addition, the current standardization efforts within the Accellera Verification Working Group will be presented to show the progress and evolution of the UVM-SystemC standard.
The intended audience of this tutorial includes managers, system and verification engineers, and architects with basic knowledge in SystemC and/or UVM, which are interested in improving their system-level verification practices.