Verification of Functional Safety for an Automotive AI Processor


Date: March 1st 
Time: 13:30-14:30 PST
Registration Access Level: ALL-ACCESS 

By: Mihajlo Katona, Veriest Solutions

This presentation is addressing the handling of random failures during the design and verification of the CEVA IPs designed to be parts of a complex automotive system. By analyzing architectural aspects of modern integrated circuits we will identify critical design features and we will review principles for verification of safety mechanisms based on an example of an AI processor for on-chip deep learning inferencing, computer vision tasks, and fusing data from multiple sensors such as radar, lidar, time-of-flight, microphones, and other inertial measurement units.

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